Integer/system instructions that were not present in the basic 80486 instruction set, but were added in various x86 processors prior to the introduction of SSE. (Discontinued instructions are not included.)
| Instruction | Opcode | Description | Ring | Added in |
|---|---|---|---|---|
RDMSR | 0F 32 | Read Model-specific register. The MSR to read is specified in ECX. The value of the MSR is then returned as a 64-bit value in EDX:EAX.[a] | 0 | IBM 386SLC,[35] Intel Pentium, AMD K5, Cyrix 6x86MX,MediaGXm, IDT WinChip C6, Transmeta Crusoe, DM&P Vortex86DX3 |
WRMSR | 0F 30 | Write Model-specific register. The MSR to write is specified in ECX, and the data to write is given in EDX:EAX.[b]Instruction is, with some exceptions, serializing.[c] | ||
RSM[42] | 0F AA | Resume from System Management Mode.Instruction is serializing. | -2 (SMM) | Intel 386SL,[43][44] 486SL,[d] Intel Pentium, AMD 5×86, Cyrix 486SLC/e,[45] IDT WinChip C6, Transmeta Crusoe, Rise mP6 |
CPUID | 0F A2 | CPU Identification and feature information. Takes as input a CPUID leaf index in EAX and, depending on leaf, a sub-index in ECX. Result is returned in EAX,EBX,ECX,EDX.[e]Instruction is serializing, and causes a mandatory #VMEXIT under virtualization.Support for CPUID can be checked by toggling bit 21 of EFLAGS (EFLAGS.ID) – if this bit can be toggled, CPUID is present. | Usually 3[f] | Intel Pentium,[g] AMD 5×86,[g] Cyrix 5×86,[h] IDT WinChip C6, Transmeta Crusoe, Rise mP6, NexGen Nx586,[i] UMC Green CPU |
CMPXCHG8B m64 | 0F C7 /1 | Compare and Exchange 8 bytes. Compares EDX:EAX with m64. If equal, set ZF[j] and store ECX:EBX into m64. Else, clear ZF and load m64 into EDX:EAX.Instruction atomic only if used with LOCK prefix.[k] | 3 | Intel Pentium, AMD K5, Cyrix 6x86L,MediaGXm, IDT WinChip C6,[l] Transmeta Crusoe,[l] Rise mP6[l] |
RDTSC | 0F 31 | Read 64-bit Time Stamp Counter (TSC) into EDX:EAX.[m][a]In early processors, the TSC was a cycle counter, incrementing by 1 for each clock cycle (which could cause its rate to vary on processors that could change clock speed at runtime) – in later processors, it increments at a fixed rate that doesn’t necessarily match the CPU clock speed.[n] | Usually 3[o] | Intel Pentium, AMD K5, Cyrix 6x86MX,MediaGXm, IDT WinChip C6, Transmeta Crusoe, Rise mP6 |
RDPMC | 0F 33 | Read Performance Monitoring Counter. The counter to read is specified by ECX and its value is returned in EDX:EAX.[m][a] | Usually 3[p] | Intel Pentium MMX, Intel Pentium Pro, AMD K7, Cyrix 6x86MX, IDT WinChip C6, AMD Geode LX, VIA Nano[q] |
CMOVcc reg,r/m | 0F 4x /r[r] | Conditional move to register. The source operand may be either register or memory.[s] | 3 | Intel Pentium Pro, AMD K7, Cyrix 6x86MX,MediaGXm, Transmeta Crusoe, VIA C3 “Nehemiah”,[t] DM&P Vortex86DX3 |
NOP r/m,NOPL r/m | NFx 0F 1F /0[u] | Official long NOP.Other than AMD K7/K8, broadly unsupported in non-Intel processors released before 2005.[v][60] | 3 | Intel Pentium Pro,[w] AMD K7, x86-64,[x] VIA C7[64] |
UD2,[y]UD2A[z] | 0F 0B | Undefined Instructions – will generate an invalid opcode (#UD) exception in all operating modes.[aa]These instructions are provided for software testing to explicitly generate invalid opcodes. The opcodes for these instructions are reserved for this purpose. | (3) | (80186),[ab] Intel Pentium[69] |
UD1 reg,r/m,[ac]UD2B reg,r/m[z] | 0F B9,0F B9 /r[ad] | |||
OIO,UD0,UD0 reg,r/m[ae] | 0F FF,0F FF /r[ad] | (80186),[ab] Cyrix 6×86,[75] AMD K5[77] | ||
SYSCALL | 0F 05 | Fast System call. | 3 | AMD K6,[af] x86-64[ag][ah] |
SYSRET | 0F 07[ai] | Fast Return from System Call. Designed to be used together with SYSCALL. | 0[aj] | |
SYSENTER | 0F 34 | Fast System call. | 3[aj] | Intel Pentium II,[ak] AMD K7,[82][al] Transmeta Crusoe,[am] NatSemi Geode GX2, VIA C3 “Nehemiah”,[an] DM&P Vortex86DX3 |